MEMS have been developed for numerous applications, including sensors such as accelerometers, gyroscopes, pressure sensors, and magnetic sensors, actuators such as atomic force microscopy (AFM) probe tips, micro mirrors, energy harvesters, resonators, motors, and passive programmable components such as Variable Capacitors, Inductors, Resistors, and RF switches or resonators. Typically, the MEMS is electrically coupled to an integrated circuit (IC), such as a complementary-metal-oxide-semiconductor (CMOS) IC, to drive the actuators or readout and amplify signals from the sensors. Conventional approaches to manufacturing combined or hybrid CMOS/MEMS have focused on either integrally forming the CMOS IC adjacent to a MEMS on a shared surface of a silicon wafer or substrate, or forming the CMOS IC and MEMS on separate substrates and bonding the MEMS substrate over a cavity formed in the CMOS IC substrate followed by partial removal of the MEMS substrate to expose pads on the CMOS IC. Although both approaches can provide hybrid CMOS/MEMS neither are wholly satisfactory.
In particular, integrally forming the CMOS IC and MEMS on a shared silicon substrate is problematic as the thin film functional layers of the MEMS tend to have thermal properties incompatible with those of the CMOS IC, and as a result require expensive calibration and compensation techniques, or large yield loss of the CMOS due to damage caused during processing. In addition, because the MEMS is not covered and protected at the wafer or substrate level, there is substantial risk of damaging the MEMS during fabrication of the CMOS IC and/or during die singulation.
Bonding the MEMS substrate over a cavity formed in the CMOS IC substrate is problematic in that the cavity wastes CMOS silicon area and the wet etch or deep reactive ion etch (DRIE) commonly used to form the cavity could damage CMOS circuitry (e.g., electrostatic damage, overheating damage), lowering the yield. Moreover, the MEMS substrate and CMOS IC substrate are bonded using processes that requires expensive equipment, is difficult to control, and often results in incomplete die bond formation across wafer including center or edge effects, lowering bonding yield. In addition, these bonding processes are generally non-compatible with typical CMOS foundry processes, and exposing pads on the CMOS IC requires either sawing or mechanical removal of excess silicon, hence lowering yield.
Accordingly there is a need for a wafer level integration of MEMS and CMOS ICs that is compatible with both MEMS and CMOS foundry processes, does not require expensive or exotic processing equipment or techniques, and provides a hermetically sealed package at wafer level with electrical connections to the outside of the sealed package, and can be singulated at die level, without reducing yield.